1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it is concerned with a semiconductor device including a field effect transistor and a bipolar transistor and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
Conventionally, a BiCMOS element has been known as an element which allows high speed operation of a bipolar element, and high integration and low power consumption of a CMOS element.
FIG. 35 is a sectional view showing a semiconductor device having a conventional BiCMOS element. Referring to FIG. 35, in the semiconductor device including the conventional BiCMOS elements a P channel MOS transistor, an N channel MOS transistor, and an NPN bipolar transistor are formed adjacent to each other on a p.sup.- type semiconductor substrate 101.
In the P channel MOS transistor region, an n.sup.+ buried layer 102a is formed on p type semiconductor substrate 101. An n.sup.- layer 103b is formed on n.sup.+ buried layer 102a. p type source/drain regions 120a and 120b are formed apart a predetermined distance from each other so as to sandwich a channel region on a main surface of n.sup.- layer 103b. A polycrystalline silicon layer 111 is formed on the channel region with a gate oxide film 110 interposed therebetween. A tungsten silicide layer 112 is formed on polycrystalline silicon 111. Polycrystalline silicon layer 111 together with tungsten silicide layer 112 forms a gate electrode. A sidewall insulating film 113 is formed on both sides of polycrystalline silicon layer 111 and tungsten silicide layer 112. Thus, the P channel MOS transistor is formed of source/drain regions 120a, 120b, polycrystalline silicon layer 111 and tungsten silicide layer 112.
In the N channel MOS transistor region, a p.sup.+ layer 102b is formed on p type semiconductor substrate 101. A p.sup.- layer 104 is formed on p.sup.+ layer 102b. High concentration source/drain regions 108a and 108b are formed apart a predetermined distance from each other so as to sandwich a channel region on a main surface of p.sup.- layer 104. Low concentration source/drain regions 109a and 109b are respectively formed on the channel region side of high concentration source/drain regions 108a and 108b. The source/drain regions of a LDD (Lightly Doped Drain) structure are formed of those high concentration source/drain regions 108a, 108b and those low concentration source/drain regions 109a, 109b.
In the NPN bipolar transistor region, n.sup.+ buried layer 102a is formed on p type semiconductor substrate 101. An n.sup.- collector layer 103a is formed on n.sup.+ buried layer 102a. An n.sup.+ collector extraction layer 105 is formed continuously with n.sup.- collector layer 103a. External base layer 114 is formed on a main surface of n.sup.- collector layer 103a. An intrinsic base layer 115 is formed surrounded by external base layer 114. An emitter layer 116 is formed on a main surface of intrinsic base layer 115. A base extraction electrode layer 117 is formed electrically connected to external base layer 114. An insulating film 118 is formed on base extraction electrode layer 117. Sidewall insulating film 113 is formed on both sides of base extraction electrode layer 117 and insulating film 118. An emitter electrode layer 119 is formed electrically in connection with emitter layer 116.
In a boundary region between the NPN bipolar transistor region and the N channel MOS transistor formed an element isolation insulating film 107. An isolation layer 106 is formed under element isolation insulating film 107. Also, element isolation insulating film 107 is formed in the boundary region between the N channel MOS transistor and the P channel MOS transistor. Element isolation insulating film 107 is also formed between external base layer 114 and n.sup.+ collector extraction layer 105 in the NPN bipolar transistor region.
FIGS. 36-45 are sectional views showing a manufacturing process of the semiconductor device having the conventional BiCMOS element shown in FIG. 35. Referring to FIGS. 36-45, description will be made on the manufacturing process of the conventional semiconductor device.
First, n.sup.+ buried layer 102a and p.sup.+ buried layer 102b are formed on p type semiconductor substrate 101, (see FIG. 35). n.sup.- collector layer 103a is formed on n.sup.+ buried layer 102a in the NPN bipolar transistor region. At the same time, n.sup.- layer 103b is formed on n.sup.+ buried layer 102a in the P channel MOS transistor. p.sup.- layer 104 is formed on p.sup.+ buried layer 102b. Then, as shown in FIG. 36, isolation layer 106 is formed in the boundary region between the NPN bipolar transistor and the N channel MOS transistor. Also, element isolation insulating film 107 is formed by the LOCOS (Local Oxidation of Silicon) method in the boundary region between the P channel MOS transistor and the N channel MOS transistor, between the N channel MOS transistor and NPN bipolar transistor, respectively, and in a predetermined region on n.sup.- layer 103a in the NPN bipolar transistor region. After that, gate oxide film 110 is formed on the entire surface, and then the gate oxide film in the NPN bipolar transistor region (not shown) is removed.
A p type polycrystalline silicon layer 117 having p type impurity doped thereinto is formed on the entire surface by the CVD method to have a thickness of about 2000 .ANG.. Insulating film 118 is formed on p type polycrystalline silicon layer 117 by the CVD method to have a thickness of about 3000 .ANG.. A resist 130 is formed at a predetermined region oil insulating film 118. Insulating film 118 and p type polycrystalline silicon film 117 are etched anisotropically using resist 130 as a mask. Whereby base extraction electrode layer 117, made of p type polycrystalline silicon film, and insulating film 118 are formed as shown in FIG. 37. Then, resist 130 is removed. After that, heat treatment is carried out such that p type impurity is thermally diffused from base extraction electrode layer (p type polycrystalline silicon layer) 117 toward n.sup.- collector layer 103a, thereby forming external base layer 114.
Next, as shown in FIG. 38, a thin oxide film 132 having a thickness of about 200 .ANG. is formed in the NPN bipolar transistor region. n type polycrystalline silicon layer 111 is formed on the entire surface by the CVD method to have a thickness of about 2000 .ANG.. Tungsten silicide layer 112 is formed on N type polycrystalline silicon layer 111 to have a thickness of about 2000 .ANG.. A resist 131 is formed at a predetermined region on tungsten silicide layer 112. Then, tungsten silicide layer 112 and N type polycrystalline silicon layer 111 are etched anisotropically using resist 131 as a mask. Whereby a patterned N type polycrystalline silicon layer 111 and tungsten silicide layer 112 are formed as shown in FIG. 39. The N type polycrystalline silicon layer 112 together with tungsten silicide layer 112 serves as a gate electrode. Then, resist 131 is removed.
Next, a resist 133 is formed to cover portions other than the NPN bipolar transistor region. p type impurity is ion-implanted into the region serving as the intrinsic base layer of the NPN transistor using resist 133 as a mask. Resist 133 is then removed.
After that, as shown in FIG. 41, a resist 134 is formed to cover portions other than the N channel MOS transistor region. n type impurity is ion-implanted into the N channel MOS transistor region using resist 134 as a mask. Resist 134 is then removed.
After formation of the insulating film on the entire surface, anisotropic etching is carried out to form sidewall insulating film 113 as shown in FIG. 42.
Next, a resist 135 is formed to cover regions other than the N channel MOS transistor region. n type impurity is ion-implanted at a high concentration into the N channel MOS transistor region using resist 135 as a mask. Resist 135 is then removed.
As shown in FIG. 44, a resist 136 is formed to cover regions other than the P channel MOS transistor region. p type impurity is ion-implanted into the P channel MOS transistor region. Resist 136 is then removed. Then, heat treatment is conducted to electrically activate the ion-implanted impurity. Thus, as shown in FIG. 45, intrinsic base layer 115, high concentration source/drain regions 108a, 108b, low concentration source/drain regions 109a, 109b, and source/drain regions 120a, 120b are formed.
After that, emitter electrode 119 made of the N type polycrystalline silicon including N type impurity is formed as shown in FIG. 35. Heat treatment is conducted to diffuse n type impurity from emitter electrode 119 toward intrinsic base layer 115, thus forming emitter layer 116. Consequently, the semiconductor device including the conventional BiCMOS element is formed.
In the manufacturing method of the above-described conventional semiconductor device, gate oxide film 110 is damaged during anisotropic etching of insulating film 118 and P type polycrystalline silicon layer 117 (see FIGS. 36-37). Therefore, when the N channel MOS transistor and the P channel MOS transistor are formed, a leak current tends to be flown to the channel region from the gate electrode through gate oxide film 110. As a result, the electrical characteristic of the N channel and the P channel MOS transistors is deteriorated.
Further, in the method of manufacturing the conventional semiconductor device, external base layer 114 is formed by heat treatment in the step shown in FIG. 37, and then heat treatment is again carried out in the step shown in FIG. 45 to form intrinsic base layer 115, high concentration source/drain regions 108a, 108b, low concentration source/drain regions 109a, 109b, and source/drain regions 120a, 120b. At this time, external base layer 114 is also affected by the heat treatment for forming intrinsic base layer 115 and the like shown in FIG. 45. As a result, external base layer 114 is further diffused to deepen its junction depth. As the depths of external base layer 114 becomes deeper, the junction area between the external base and the collector becomes larger, whereby the junction capacitance between the external base and the collector increases. Also, as the depths of external base layer 114 becomes deeper, the distance between external base layer 114 (see FIG. 35) and n.sup.+ buried layer 102a becomes narrower, whereby the capacitance between the external base and n buried layer increases. Consequently, the parasitic capacitance increases because of the increased junction capacitance between the external base and the collector and the increased capacitance between the external base and n.sup.+ buried layer. The increased parasitic capacitance causes reduction of the operating speed of the NPN bipolar transistor.